The present invention relates to MOS field-effect transistors and a process for fabricating MOS field-effect transistors. More specifically, the present invention relates to MOS field-effect transistors having fine lateral impurity diffusion profiles, and processes for achieving, fine structures.
FIG. 3 shows a conventional process (disclosed in Japanese patent provisional publication No. 56-10971, for example) for fabricating a vertical MOSFET, using double diffusion technique.
At a step (A) of FIG. 3, a high resistivity epitaxial layer 2 of a first conductivity type is formed by epitaxial growth on a low resistivity substrate 1. In this example, the first conductivity type is the n type, and a second conductivity type opposite to the first type is the p type. Thus, a semiconductor body consisting of the substrate 1 and the epitaxial layer 2 is obtained. Then, a gate oxide layer 3 is formed on the high resistivity epitaxial layer 2 by thermal oxidation. Then, a polycrystalline silicon layer 4 is formed on the gate oxide layer 3 by CVD.
At a next step (B) of FIG. 3, a predetermined area of an upper surface of the high resistivity epitaxial layer 2 is exposed by patterning the gate insulating layer 3 and the polycrystalline silicon layer 4 in a manner of self alignment by lithography.
At a step (C), a base region 5 of the second conductivity type which is the p type in this example is formed by selectively doping the epitaxial layer 2 from the upper surface through a diffusion window formed at the step (B). The doping is performed, in this example, by ion implantation and thermal diffusion. During this step, the diffusion proceeds not only downward from the upper surface of the epitaxial layer 2, but also sideways from the diffusion window. Therefore, the base region 5 extends not only vertically from the upper silicon surface, but also the base region 5 extends laterally from the diffusion window under the gate oxide layer 3 and the polycrystalline silicon layer 4.
The method of forming a gate electrode beforehand, and then forming a doped region such as the base region is known as a self alignment technique. In this technique, the gate electrode is used as a mask, so that the mask is aligned automatically, and accordingly, the accuracy in dimension is greatly improved.
At a step (D), a source region of the first conductivity type such as the n type is formed by selectively doping the base region 5 by ion implantation and thermal diffusion. The source region 6 extends into the base region 5 from the upper surface.
At a step (E), a drain electrode D is formed on the bottom surface of the semiconductor body, the gate electrode G is completed, and a topside source electrode S is formed. The source electrode S is formed over the source region 6 and the base region 5, and connected to both regions.
In this process, a peripheral portion of the base region 5 is formed underneath the gate oxide layer 3 and the polycrystalline silicon layer 4, and this peripheral portion of ,the base region 5 acts as a channel region of the field-effect transistor. The length of the peripheral portion of the base region 5 is determined by the distances of the lateral diffusion of the base region 5 and the source region 6, so that the length can be made very small. Thus, very short channel lengths can be attained by the double diffusion technique.
FIG. 4 shows an equivalent circuit of the vertical MOSFET fabricated by the process of FIG. 3, FIG. 5 shows the characteristic relationship between drain current and drain voltage of the MOSFET.
As shown in FIG. 4, there is formed, in the base region 6, a resistance 7, having a value rb, directly under the source region 6. Electrons diffusing in the base region 5 under the source region 6 receive this resistance until they reach the source electrode.
In FIG. 5, Vd.sub.SB is a secondary breakdown voltage. When the drain voltage beyond the secondary breakdown voltage is applied, the vertical MOSFET loses its ability to perform the required function because of breakdown. A relation between the second breakdown voltage Vd.sub.SB and the resistance 7 is disclosed in IEEE Trans. Electron Devices, Vol. ED-29, No. 8, pp. 1287-1293, Aug. 1982 "Secondary Breakdown of Vertical Power MOSFETs", Chen Ming Hu, Min Hwa Chi. In order to increase the secondary breakdown voltage, it is desirable to decrease the value rb of the resistance 7.
In the conventional fabrication process, however, it is difficult to sufficiently decrease the length of the source region 6 because the source region 6 is formed by lithography, and the length of the source region 6 is determined by the accuracy of the lithography. Therefore, the vertical MOSFET obtained by this conventional process has the resistance 7 of a high value rb because of the relatively long source region 6. As a result, the secondary breakdown voltage Vd.sub.SB is low, and the safe operating area of the device is narrow.